Wafer warpage during the processing of semiconductor wafers is an ongoing issue which, when not contained, results in many undesirable consequences that increase costs. Some typical undesirable consequences may be simply having sections of the lithography being out of focus, causing imperfection in the integrated circuits being formed on the wafer, which affects the final usable device yield. In more severe examples, complete breakage of the wafer during processing may result, causing loss of the wafer and the economic loss of all the value of prior processing. In the cases where a wafer breakage occurs, the down time associated with cleaning the processing tool from all the wafer pieces further reduces throughput and increases costs. In extreme cases, the processing tool itself can be damaged resulting in repair costs in addition to the down time for cleaning the tool.
Some factors that have increased the significance and incidence of wafer warpage include the increase in wafer diameters from 200 mm to 300 mm, the ability and requirement to thin the wafers during production so that the finished integrated circuits will fit in thinner packages, and the additional complexity of fabrication processes that build comparatively more layers and which perform more heat treatments, increasing thermal stress.
Of special interest is the fabrication of Micro Electrical Mechanical (MEMs) devices. Some processes in the fabrication of the MEMs devices involve performing deep etches in the final stages of semiconductor processing, after much of the costly fabrication steps have already been completed. Some of these deep etches are performed on the backside of the wafer, that is, after the MEMs devices and other circuitry are processed on the front side, the backside is processed while the completed devices are disposed on the front side. These deep etches can remove a substantial portion of the wafer material which may also result in the reduction of structural integrity of the wafer. One example of such an etch is a process known as Deep Reactive Ion Etching (DRIE) which is capable of performing very deep, high aspect ratio, anisotropic etches in silicon and polycrystalline silicon (polysilicon).
FIG. 1A depicts a top view of a wafer, and FIG. 1B depicts a cross section of the wafer of FIG. 1A illustrating wafer warpage following a deep etch, and FIG. 1C depicts an alternate warpage in the cross section of FIG. 1A. A top view 100 illustrates a semiconductor wafer 102 with a number of rows and columns of multiple integrated circuits (ICs) 104. In FIG. 1A the wafer 102 is depicted during fabrication while the integrated circuits are still mechanically joined. The cross sections labeled FIG. 1B and FIG. 1C illustrate two of the possible wafer warpage effects that can occur. In FIG. 1B, wafer 102 is shown with the edges of the wafer lifted up away from the ideal flat line 122a. In another example, FIG. 1C, wafer warpage is depicted as an “S” type warpage where the left side is lifted away from the ideal flat line 122b and the right side of wafer 102 is depressed below the ideal flat line 122b. These 2 example warpages show warpage across the entire wafer, however, the wafer 102 can develop localized warpage where one area is flat and another is warped. The wafer warpage can affect subsequent processing steps and cause failed devices due to lithography errors, alignment errors or other process errors. In extreme cases the entire wafer can be lost due to the warpage.
Improvements in the manufacture of semiconductor wafers to reduce or eliminate problems associated with wafer warpage are therefore needed and desired. Reduction or elimination of wafer warpage in processes that include backside etches, such as in producing MEMS devices with deep cavities, are particularly needed.